The present invention relates to BiCMOS (i.e., bipolar and complementary metal oxide semiconductor (CMOS)) technology, and more particularly to a method of fabricating a polysilicon to polysilicon, i.e., poly-poly, capacitor integrated with a SiGe heterojunction bipolar transistor.
In the field of semiconductor device manufacturing, CMOS and BiCMOS technologies have been widely used for integrating highly complex analog-digital subsystems onto a single chip. In such subsystems, high precision capacitors are typically required.
Several types of capacitors are presently available including diffusion-poly capacitors, poly-poly capacitors and metal-metal capacitors. In order to meet the demand for high precision capacitors in today""s generation of integrated devices, poly-poly capacitors have been increasingly used.
Despite its high precision, a poly-poly capacitor is a compromise between high cost and ideal capacitor characteristics since it is relatively easy to construct, and has electrical characteristics that are better than diffusion-poly capacitors, but inferior electrical characteristics to metal-metal capacitors. However, a metal-metal capacitor is much more difficult to fabricate than are poly-poly capacitors.
Moreover, poly-poly capacitors are known to have a more linear V-C relationship than MOS (i.e., diffusion-poly) capacitors. The dielectric for MOS capacitors results from an oxide that is thermally grown over a highly doped diffusion region. In contrast, the dielectric for a poly-poly capacitor is generally a deposited chemical vapor deposition (CVD) oxide and reliability requirements cause the resulting oxide to be thicker than can be realized with a thermal oxide. Therefore, higher capacitance values generally result for MOS capacitors than poly-poly capacitors.
Although various methods of forming poly-poly capacitors are known, most prior art methods are not suitable for integration with BiCMOS processing schemes. In view of the BiCMOS integration problem with prior art methods, there is a continued need for developing a new and improved method of fabricating a poly-poly capacitor utilizing existing polysilicon layers and masking steps employed in conventional BiCMOS processes. Specifically, it would be highly beneficial if a method of fabricating a poly-poly capacitor could be developed in which the bottom plate of the capacitor was formed from a gate of the MOS transistor, and wherein the top plate of the capacitor was formed from the base region of a heterojunction bipolar transistor.
One object of the present invention is to provide a method of fabricating a poly-poly capacitor for use in CMOS or BiCMOS integrated circuits that is not complicated or expensive.
Another object of the present invention is to provide a method of manufacturing a poly-poly capacitor utilizing existing polysilicon and masking steps, thereby achieving the integration of the poly-poly capacitor into a BiCMOS device at a low cost.
A yet further object of the present invention is to provide a method of fabricating a poly-poly capacitor utilizing steps and structures that are typically used to form the gate of the MOS transistor and SiGe base structure of the bipolar transistor in a BiCMOS process.
These and other objects and advantages are achieved by utilizing the inventive method in which the lower polysilicon layer of the capacitor is formed during deposition of the CMOS gate electrode and the upper SiGe polysilicon layer of the capacitor is formed during the growth of the base region of the SiGe heterojunction bipolar transistor. Broadly speaking, the inventive method thus comprises forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.
Specifically, and in a first embodiment of the present invention, the inventive method comprises the steps of:
(a) forming a first polysilicon layer over a portion of an isolation region in a device region in which a poly-poly capacitor is to be formed;
(b) forming first nitride spacers about said first polysilicon layer;
(c) depositing a nitride layer over said first polysilicon layer and said first nitride spacers;
(d) implanting ions of a first conductivity type into said first polysilicon layer so as to form a lower electrode of said poly-poly capacitor;
(e) removing portions of said nitride layer so as to form second nitride spacers and to expose a portion of said lower electrode;
(f) forming a film stack on at least said exposed portion of said lower electrode, said film stack comprising an oxide layer, a second layer of polysilicon and a layer of SiGe;
(g) implanting ions of a second conductivity type that are different from said first conductivity type into said layer of SiGe and said second layer of polysilicon;
(h) etching at least said layer of SiGe and said second layer of polysilicon so as to form an upper electrode of said poly-poly capacitor; and
(i) saliciding all exposed surfaces of said upper electrode.
It is noted that the above processing steps are used in forming a high capacitance poly-poly capacitor. Alternatively, a patterned protective nitride layer can be formed on portions of the exposed upper electrode prior to saliciding the structure.
In accordance with the second embodiment of the present invention, in which a high voltage device is formed, the method of the present invention comprises the steps of:
(a) forming a first polysilicon layer over a portion of an isolation region in a device region in which a poly-poly capacitor is to be formed;
(b) forming first nitride spacers about said first polysilicon layer;
(c) depositing a nitride layer over said first polysilicon layer and said first nitride spacers;
(d) implanting ions of a first conductivity type into said first polysilicon layer so as to form a lower electrode of said poly-poly capacitor;
(e) forming a film stack on at least said nitride layer, said film stack comprising an oxide layer, a second layer of polysilicon and a layer of SiGe;
(f) implanting ions of a second conductivity type that are different from said first conductivity type into said layer of SiGe and said second layer of polysilicon;
(g) etching at least said layer of SiGe and said second layer of polysilicon so as to form an upper electrode of said poly-poly capacitor; and
(h) saliciding all exposed surfaces of said upper electrode.
As is the case in the first embodiment, a patterned protective nitride layer can be formed on at least a portion of the exposed upper electrode prior to salicidation.
It is emphasized herein that the doped first layer of polysilicon serves as the lower electrode of the inventive poly-poly capacitor, whereas the doped SiGe layer together with the doped second layer of polysilicon serve as an upper electrode of the poly-poly capacitor.